View ADL5906-EVALZ_6481906.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

10 mhz to 10 ghz 67 db trupwr detector data sheet adl5906 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringeme nts of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features accurate rms - to - dc conversion from 1 0 mhz to 10 ghz single - ended 1 .0 db dynamic range: 6 7 db at 2.14 ghz no balun or external input match ing required response i ndependent of w aveform t ypes , such as gsm - edg e /cdma/w - cdm a/td - scdma/wimax/lte logarithmic s lope : 55 mv/db temperature stability: <1 db from ?40c to + 12 5c operating t emperature : ?55c to +125c supply v oltage: 4. 7 5 v to 5. 2 5 v sleep c urrent: 250 a pin compatible with adl5902 and ad8363 applications power amplifier linearization/control loops transmitter signal strength indication (tssi) rf instrumentation functional block dia gram t adj/ pwdn nic vref vtgt crms vrms v se t vt e m p nic rfin? rfin+ ni c gnd1 gnd2 epad x 2 bias and power down contro l 1 i tgt linear-in-db vg a (neg a tive slope) i sqr 26pf 2 vpos1 v p o s2 3 4 1 1 1 0 9 5 6 7 8 1 6 1 5 1 4 1 3 adl5906 1 2 x 2 v ref 2.3v temper a ture sensor g = 5 1 1287-001 figure 1. general description the adl5906 is a true rms responding power detector that has a 67 db measurement range when driven with a single - ended 50 source. the easy to use input makes the adl5906 frequency versatile by eliminating th e need for a balun or any other form of external i n put tuning for operation up to 10 ghz. the adl5906 provides a solution in a variety of high frequency systems requiring an accurate rms measurement of signal power . the adl5906 can operate from 10 mhz to 10 ghz and can accept inputs from ? 65 dbm to +8 dbm with varying crest factors and bandwidths , such as g sm - edge, cdma, w - cdma, td - scdma, wimax, and ofdm - based lte carriers. in addition, its temperature stability over the broad temperature range of ?55c to +125c makes it ideall y suited f or a wide array of communications, military, industrial, and instrumentation applications. used as a power measurement device, vrms is connected to vset. the output is then proportional to the logarithm of the rms value of the input. in other words, the reading is presented directly in decibels and is scaled 1.1 v per decade, or 55 mv/db; other slopes are easily arranged. in controller mode , the voltage applied to vset determines the power level required at the input to null the deviation from the setpoin t. the output buffer can provide high load currents. requiring only a single supply of 5 v and a few capacitors, it is easy to use and capable of being driven single - ended or with a balun for differential input drive. the adl5906 has a low 250 a sleep current when powered down by a logic high applied to the pwdn pin. it powers up within approximately 1. 4 s to its nominal operating current of 68 ma at 25c . the adl5906 is supplied in a 4 mm 4 mm, 16- lead lfcsp , and it is pi n compatible with the adl5902 and the ad83 63 trupwr ? rms detector s . this feature allows the designer to create one circuit layout for projects requiring different dynamic ranges. a f ully populated rohs - c ompliant evaluation board is available.
adl5906 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 16 square law detector and amplitude t arget .............................. 16 rf input interface ...................................................................... 17 temperature sensor interface ................................................... 17 v ref interface ........................................................................... 17 temperature compensation interface ..................................... 18 power - down interface ............................................................... 19 vset interface ............................................................................ 19 output interface ......................................................................... 19 vtgt interface .......................................................................... 19 basis for error calculations ...................................................... 20 measurement mode basic connections .................................. 20 setting v tadj ................................................................................ 20 setting v tgt ................................................................................. 21 choosing a value for c rms ......................................................... 21 output voltage scaling .............................................................. 22 system calibration and error calculation .............................. 24 using v temp to improve intercept temperature drift ........... 25 description of characterization ............................................... 27 evaluation board ............................................................................ 28 evaluation board assembly drawings .................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 3 /1 3 revision 0: initial version
data sheet adl5906 rev. 0 | page 3 of 32 specifications vpos1 = vpos2 = 5 v, t a = 25c, single - ended input drive, r t = 60.4 ?, vrms connected to vset, v tgt = 0.8 v, c rms = 0.1 f. negative current values imply that the adl5906 is sourcing current out of the indicate d pin. table 1 . parameter test conditions /comments min typ max unit overall function frequency range 1 0 to 10, 000 mhz rf input interface rfin+ , pin rfin ? (pin 14, pin 15) , ac - coupled input impedance single - ended dr ive, 50 mhz 2500 ? common - mode voltage 2.5 v 100 mhz 1.0 db dynamic range c ontinuous wave (cw) input, t a = 25c 6 2 db maximum input level, 1.0 db calibration at ? 55 dbm, ? 40 dbm, and 0 dbm 2 dbm minimum input level, 1.0 db calibratio n at ?55 dbm, ?40 dbm, and 0 dbm ? 60 dbm deviation vs. temperature deviation from output at 25c , v tadj = 0.35 v ?40c < t a < +85c; p in = 0 dbm ? 0.8 / + 0.2 db ?40c < t a < +85c; p in = ? 45 dbm ? 0.8 /+ 0.4 db ? 55 c < t a < +125c; p in = 0 dbm ? 1.3 /+ 0.2 db ? 55 c < t a < +125c; p in = ? 45 dbm ? 1.2 /+ 0.6 db logarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm and 0 dbm 59 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm and 0 dbm ? 64 dbm 7 00 mhz 1.0 db dynamic range cw input, t a = 25c 62 db maximum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm 2 dbm minimum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm ? 60 dbm deviation vs. temperature deviation from output at 25c , v tadj = 0.35 v ?40c < t a < +85c; p in = 0 dbm ? 0.9 /+ 0.3 db ?40c < t a < +85c; p in = ?45 dbm ? 0.9 /+ 0.4 db ?55c < t a < +125c; p in = 0 dbm ? 1.5 /+ 0.3 db ?55c < t a < +125c; p in = ?45 dbm ? 1.3 /+ 0.7 db logarithmic s lope ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm , and 0 dbm 59 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm and 0 dbm ? 65 dbm 9 00 mhz 1.0 db dynamic range cw input, t a = 25c 63 db maximum input level, 1. 0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm 3 dbm minimum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm ? 60 dbm deviation vs. temperature deviation from output at 25c , v tadj = 0.35 v ?40c < t a < +85c; p in = 0 dbm ? 0.8 / + 0.3 db ?40c < t a < +85c; p in = ?45 dbm ? 0.9 /+ 0.4 db ?55c < t a < +125c; p in = 0 dbm ? 1.4 /+ 0.3 db ?55c < t a < +125c; p in = ?45 dbm ? 1.4 /+ 0.8 db logarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm and 0 dbm 59 mv/db loga rithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm ? 65 dbm deviation from cw response ( ? 45 dbm to ? 5 dbm) 12.16 db peak -to - rms ratio (four- carrier w - cdma ) ?0.1 db 11.58 db peak - to - rms ratio (lte tm1, one - carrier , 20 mhz ban dwidth ) ?0.2 db 10.56 db peak -to - rms ratio (w - cdma) 0.05 db 7.4 db peak -to - rms ratio (64 qam) ?0.1 db
adl5906 data sheet rev. 0 | page 4 of 32 parameter test conditions /comments min typ max unit 1900 mhz 1.0 db dynamic range cw input, t a = 25c 66 db maximum input level, 1.0 db cal ibration at ?55 dbm, ?40 dbm, and 0 dbm 6 dbm minimum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm ?60 dbm deviation vs. temperature deviation from output at 25c, v tadj = 0.35 v ?40c < t a < +85c; p in = 0 dbm ?0.8/+0.2 db ?40c < t a < +85c; p in = ?45 dbm ?0.8/+0.5 db ?55c < t a < +125c; p in = 0 dbm ?1.4/+0.2 db ?55c < t a < +125c; p in = ?45 dbm ?1.2/+0.9 db logarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm 57 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm ? 65 dbm 2140 mhz 1.0 db dynamic range cw input, t a = 25c 67 db maximum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm 7 dbm minimum input level, 1.0 db c alibration at ?55 dbm, ?40 dbm, and 0 dbm ?60 dbm deviation vs. temperature deviation from output at 25c, v tadj = 0.35 v ?40c < t a < +85c; p in = 0 dbm ?0.8/+0.3 db ?40c < t a < +85c; p in = ?45 dbm ?0.8/+0.6 db ?55c < t a < +125c; p in = 0 dbm ?1.3/+0.3 db ?55c < t a < +125c; p in = ?45 dbm ?1.2/+0.9 db logarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm and 0 dbm 56 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ? 40 dbm and 0 dbm ? 65 dbm deviation from cw response ( ? 45 dbm to ? 5 dbm) 12.16 db peak -to - rms ratio (four- carrier w - cdma ) ?0.1 db 11.58 db peak - to - rms ratio (lte tm1, one - carrier , 20 mhz bandwidth ) 0.1 db 10.56 db peak -to - rms rat io (one - carrier w - cdma) 0.1 db 7.4 db peak -to - rms ratio (64 qam) ?0.1 db 2600 mhz 1.0 db dynamic range cw input, t a = 25c 68 db maximum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm 8 dbm minimum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm ?60 dbm deviation vs. temperature deviation from output at 25c, v tadj = 0.4 v ?40c < t a < +85c; p in = 0 dbm ?0.9/+0.3 db ?40c < t a < +85c; p in = ?45 dbm ?1/+0.5 db ?55c < t a < +1 25c; p in = 0 dbm ?1.4/+0.3 db ?55c < t a < +125c; p in = ?45 dbm ?1.4/+0.8 db logarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm 55 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm ? 65 dbm 3500 mhz 1.0 db dynamic range cw input, t a = 25c 65 db maximum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm 5 dbm minimum input level, 1.0 db calibration at ?55 dbm, ?40 dbm, and 0 dbm ?60 dbm deviation vs. te mperature deviation from output at 25c , v tadj = 0.45 v ?40c < t a < +85c; p in = 0 dbm ?1.5/0 db ?40c < t a < +85c; p in = ?45 dbm ?1/+0.3 db ?55c < t a < +125c; p in = 0 dbm ?1.5/0 db ?55c < t a < +125c; p in = ?45 dbm ?1.4/+0.4 db l ogarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm 52 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm ? 64 dbm
data sheet adl5906 rev. 0 | page 5 of 32 parameter test conditions /comments min typ max unit 5800 mhz 1.0 db dynamic range cw input, t a = 25c 57 db maximum inp ut level, 1.0 db calibration at ?50 dbm, ?40 dbm, and 0 dbm 3 dbm minimum input level, 1.0 db calibration at ?50 dbm, ?40 dbm, and 0 dbm ?54 dbm deviation vs. temperature deviation from output at 25c , v tadj = 1 v ?40c < t a < +85c; p in = 0 dbm ? 2.4 /+0 db ?40c < t a < +85c; p in = ?45 dbm ?1.4/ - 0.2 db ?55c < t a < +125c; p in = 0 dbm ?3.6/+0 db ?55c < t a < +125c; p in = ?45 dbm ?2.1/ - 0.2 db logarithmic slope ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm 42 mv/db logarithmic intercept ?65 dbm < p in < + 10 dbm; calibration at ?40 dbm and 0 dbm ? 60 dbm output interface vrms (pin 6) output swing, controller mode swing range minimum, r l 500 ? to ground 0.05 v swing range maximum, r l 500 ? to ground 3. 92 v current source/sink capability 10/10 ma rise time p in = off to ?10 dbm, 10% to 90%, c rms = 1 nf 0.1 s fall time p in = ?10 dbm to off, 90% to 10%, c rms = 1 nf 14.6 s setpoint input vset (pin 7) voltage range log conformance error 1 db, minimum 2.14 ghz 3.92 v log conformance error 1 db, maximum 2.14 ghz 0.4 v input resistance 72 k? logarithmic scale factor f = 2.14 ghz 56 mv/db logarithmic intercept f = 2.14 ghz ? 65 dbm temperature compensation tadj/pwdn (pin 1) input voltage range 0 v pos v input bias current v tadj = 0.35 v 5 a input resistance v tadj = 0.35 v 70 k ? voltage reference vref (pin 11) output voltage p in = ?55 dbm 2. 3 v temperature se nsitivity 25 c t a 125c ? 0.12 mv/c ?55 c t a +25c 0.07 mv/c short - circuit current source/ sink capability 25 c t a 125c 4/0.05 ma ?55 c t a +25c 3/0.05 ma voltage regulation t a = 25 c, i load = 2 ma ? 0.4 % temperature reference vtemp (pin 8) output voltage t a = 25 c, r l 10 k? 1.4 v temperature coefficient ?40 c t a +125c, r l 10 k? 4.8 mv/c shor t - circuit current source/ sink capability 25 c t a 125c 4/0.05 ma ?55 c t a +25c 3/0.05 ma voltage regulation t a = 25 c, i load = 1 ma ? 2.8 % rms target interface vtgt (pin 12) input voltage range 0.2 2.5 v input bias current v tgt = 0.8 v 8 a input resistance 100 k? power - down interface vtadj/pwdn (pin 1) voltage level to enable v pwdn decreasing 1. 3 v voltage level to disable v pwdn increasing 1. 4 v input bias current v pwdn = 5 v 72 a v pwdn = 0 v 0.1 a e nable time v pwdn low to v rms , 10% to 90%, c rms = 1 nf, p in = 0 dbm 1. 4 s disable time v pwdn high to v rms , 90% to 10%, c rms = 1 nf, p in = 0 dbm 1.0 s
adl5906 data sheet rev. 0 | page 6 of 32 parameter test conditions /comments min typ max unit power supply interface vpos1, vpos2 (pin 3, pin 10) supply voltage 4. 7 5 5 5. 2 5 v quiescent c urrent t a = 25c, p in < ?60 dbm 68 ma t a = 125c, p in < ?60 dbm 86 ma power - down current v pwdn > 1.4 v 250 a
data sheet adl5906 rev. 0 | page 7 of 32 absolute maximum rat ings table 2 . parameter rating supply voltage, vpos 1, vpos2 5. 2 5 v input average rf power 1 21 dbm equivalen t voltage, sine w ave input 2.51 v p -p internal power dissipation 550 mw jc 2 10.6 c/w jb 2 35.3 c/w ja 2 57.2 c/w jt 2 1.0 c/w jb 2 34 c/w maximum junction temperature 150c operating temperature range ? 55 c to +125c storage temperature range ?65 c to +150c lead temperature (soldering , 60 sec) 300c 1 this is for long durations. excursions above this level, with durations much less than 1 second, are possible without damage. 2 no airflow with the exposed pad soldered to a 4 - layer jedec board. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adl5906 data sheet rev. 0 | page 8 of 32 pin configuration and function descripti ons pin 1 i nd i cat or notes 1. nic = no interna l connection. do not connect t o this pin. 2. the exposed p ad requires a good therma l and electrica l connection t o the ground of the printed circuit board (pcb). 1 t ad j/pwd n 2n ic 3vpos1 4 gnd1 11 vr ef 12 vtg t 10 vpos2 9 gnd2 5 crms 6 vrms 7 vset 8 vtemp 15 rfin? 16 n ic 14 rfin+ 13 n ic to p vi ew (not to s ca le) adl5906 1 1287-002 figure 2. pin configuration tabl e 3 . pin function descriptions pin no. mnemonic description 1 tadj/pwdn temperature compensation / shutdown . this is a dual function pin used for controlling temperature slope compensation at voltage s <1 .0 v and/or for shuttin g down the device at voltages > 1.4 v. the temperature compensation voltage is generally set by connecting this pin to vref through a resistive voltage divider (see the setting v tadj section for additional information ). see figure 46 for an equivalent circuit. 2 , 13, 16 nic no internal connect ion . do not connect to these pins. these pins are not internally connected. 3, 10 vpos 1, vpos2 power supply . because the se pins are internally shorted, they must be connected to the same 5 v power supply. the power supply to each pin must also be decoupled using 100 pf and 100 nf capacitors located as close as possible to the pins . 4, 9 gnd1, gnd2 ground . connect both gnd1 and gnd2 to system ground using a low impedance path. 5 crms rms averaging capacitor . connect a n rms averaging capacitor between crms and ground . see the choosing a value for c rms section for more information. see figure 48 for an equivalent circuit. 6 v rms rms output . i n measurement m ode, this pin is connected to vset either directly or through a resistor divider (when the slope is being increased) . in controller m ode, t his pin is used to drive the gain control input of a voltage variable attenuator (vva) or variable gain amplifier (vga) . see figure 48 for an equivalent circuit. 7 vset setpoint input . in measurement m ode, this pin is connected to vrms either directly or throug h a resistor divider. in controller m ode, the voltage applied to this pin sets the decibel value of the required rf input level to balance the automatic power control loop . see figure 47 f or an equivalent circuit. 8 v temp temperature sensor output of 1.4 v at 25 c with a c oefficient of 4.8 mv/c. see figure 43 for an equivalent circuit. 11 vref reference voltage output . this voltage reference has a nominal value of 2. 3 v. this reference output voltage can be us ed to set the voltag e to the tadj/pwdn and vtgt pin s. see figure 44 for an equivalent circuit. 12 vtgt rms target voltage . the voltage applied to this pin sets the target rf input at the output of the vga that is also the rms squaring circuit. the recommended voltage for vtgt is 0.8 v. increasing v tgt above 0.8 v degrade s the rms accuracy of the adl5906 . reducing v tg t below 0.8 v can improve the rms accuracy for signals with very high crest factors ; however, it reduce s the detection range of the adl5906 . see figure 49 for an equivalent circuit. 14 , 15 rfin+, rfin ? rf i nput s. the rf input s are normally applied single - ended with t he rf input signal ac - coupled to rfin+ and rfin ? ac - coupled to ground . see figure 42 for an equivalent circuit. epad the exposed pad on the underside of the device (epad) is also internally connected to ground and requires a good thermal and electrical connection to the ground of the printed circuit board (pcb).
data sheet adl5906 rev. 0 | page 9 of 32 typical performance characteristics v pos1 = vpos2 = 5 v, single- ended input drive, v rms connected to vset, v tgt = 0.8 v, c rms = 0.1 f, t a = +25 c ( green ), ?55c (light blue), ?40c (blue ), +85c (red) , +105c (orange), and +125c ( black ), where appropriate . e rror referred to slope and intercept at indicated calibration points . input rf signal is a sine wave (cw) , unless otherwise indicated. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 output vo lt age (v) 100mhz t o 1ghz 20mhz 10mhz p in (dbm) 1 1287-003 2ghz 3ghz 4ghz 5ghz 6ghz 7ghz 8ghz 9ghz 10ghz figure 3. typical v rms vs. input power (dbm) vs. f requency ( 10 mhz to 10 ghz) at 25 c ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age (v) p in (dbm) cw qpsk pe p = 3.8db 16 qam pe p = 6.3db 64 qam pe p = 7.4db 1 1287-104 figure 4. error from cw linear reference vs. signal modulation (qpsk, 16 qam, 64 qam), frequency = 900 mhz, c rms = 0.1 f , th ree point calibration at 0 dbm, ? 40 dbm , and ? 55 dbm ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age (v) p in (dbm) cw cdm a 2000 pe p = 1 1.02db 1c w -cdm a pe p = 10.56db 4c w -cdm a pe p = 12.08db 1 1287-005 figure 5. error from cw linear reference vs. signal modulation (cdma 2000, one - carrier w- cdma, four - carrier w- cdma), frequency = 2. 14 g hz, c rms = 0.1 f , three point calibration at 0 dbm, ?40 dbm, and ?55 db m ?20dbm 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.01 0.1 1 10 output vo lt age (v) frequenc y (ghz) ?50dbm ?10dbm 0dbm ?30dbm ?40dbm 1 1287-006 figure 6 . typical v rms vs. frequency for six rf input levels ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age (v) p in (dbm) cw qpsk pe p = 3.8db 16 qam pe p = 6.3db 64 qam pe p = 7.4db 1 1287-007 figure 7. error from cw linear reference vs. signal modulation (qpsk, 16 qam, 64 qam), frequency = 2.14 ghz , c rms = 0.1 f , three point calibration at 0 dbm, ?40 dbm, and ?55 dbm ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age (v) p in (dbm) cw l te tm1 1cr 20mhz pe p = 1 1.58db 1 1287-008 figure 8. error from cw linear reference vs. signal modulation ( lte tm1 one - carrier , 20 mhz ), frequency = 2.14 ghz , c rms = 0.1 f , three point calibration at 0 dbm, ?40 dbm, an d ?55 dbm
adl5906 data sheet rev. 0 | page 10 of 32 output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 error (db) output vo lt age (v) p in (dbm) v t adj = 0.35v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-009 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 figure 9. v rms and log conformance error vs. input level and temperature at 100 mhz output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 error (db) output vo lt age (v) p in (dbm) v t adj = 0.35v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-010 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 figure 10 . v rms and log conformance error vs. input level and temperature at 700 mhz ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output vo lt age (v) 5 p in (dbm) v t adj = 0.35v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-0 1 1 ?65 ?55 ?45 ?35 ?25 ?15 ?5 figure 11 . v rms and log conformance error vs. input level and temperature at 900 mhz ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 output vo lt age (v) p in (dbm) 1 1287-012 v t adj = 0.35v figure 12 . distribution of log conformance error with respect to v rms at 25c vs . input level and temperature at 100 mhz ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age (v) p in (dbm) 1 1287-013 v t adj = 0.35v figure 13 . distribution of log conformance error with respect to v rms at 25c vs . input level and temperature at 700 mhz output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 error (db) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) 1 1287-014 v t adj = 0.35v figure 14 . distribution of log conformance error with respect to v rms at 25c vs . input level and temperature at 900 mhz
data sheet adl5906 rev. 0 | page 11 of 32 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output vo lt age (v) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) v t adj = 0.35v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-015 figure 15 . v rms and log conformance error vs. input level and temperature at 1.9 ghz ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output vo lt age (v) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) v t adj = 0.35v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-016 figure 16 . v rms and log conformance error vs. input level and temperature at 2 .14 ghz ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output vo lt age (v) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) v t adj = 0.4v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-017 figure 17 . v rms and log conformance error vs. input level and temperature at 2.6 ghz output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 error (db) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) 1 1287-018 v t adj = 0.35v figure 18 . distribution of log conformance error with respect to v rms at 25c vs . input level and tempera ture at 1.9 gh z output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 error (db) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) 1 1287-019 v t adj = 0.35v figure 19 . distribution of log conformance error with respect to v rms at 25c vs . input level and temperature at 2.14 ghz error (db) output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) 1 1287-020 v t adj = 0.4v figure 20 . distribution of log conformance error with respe ct to v rms at 25c vs . input level and temperature at 2.6 ghz
adl5906 data sheet rev. 0 | page 12 of 32 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output vo lt age (v) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) v t adj = 0.45v calibr a tion a t 0dbm, ?40dbm, and ?55dbm 1 1287-021 figure 21 . v rms and log conformance error vs. input level and temperature at 3.5 ghz 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) v t adj = 1v calibr a tion a t 0dbm, ?40dbm, and ?50dbm 1 1287-022 figure 22 . v rms and log conformance error vs. input level and temperature at 5.8 ghz 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) output vo lt age (v) ?45 ?35 ?25 ?15 ?5 5 p in (dbm) v t adj = 1v calibr a tion a t 0dbm, ?20dbm, and ?35dbm 1 1287-023 figure 23 . v rms and log conformance error vs. input level and temperature at 8 ghz error (db) output vo lt age (v) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) 1 1287-024 v t adj = 0.45v figure 24 . distribution of log conformance error with respect to v rms at 25c vs . input level and temperature at 3.5 ghz ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?60 ?50 ?40 ?30 ?20 ?10 0 10 error (db) output vo lt age (v) p in (dbm) 1 1287-025 v t adj = 1v figure 25 . distribution of log conformance error with respect to v rms at 25c vs . input level and temperature at 5.8 ghz 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 ?35 ?25 ?15 ?5 5 output vo lt age (v) p in (dbm) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 error (db) v t adj = 1v calibr a tion a t 0dbm, ?10dbm, and ?20dbm 1 1287-026 figure 26 . v rms and log conformance error vs. input level and temperature at 10 ghz
data sheet adl5906 rev. 0 | page 13 of 32 count 1000 800 600 400 200 0 2.8 3.0 3.2 2.9 3.1 3.3 3.4 3.5 v rms (v) 1 1287-027 represents 4500 p arts figure 27 . distribution of v rms , p in = ?10 dbm, 900 mhz counts 1000 800 600 400 200 0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 v rms (v) 1 1287-028 represents 4500 p arts figure 28 . distribution of v rms , p in = ?45 dbm, 900 mhz 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 35 40 45 50 output vo lt age (v) time (s) rf burst pulse 0dbm ?10dbm ?20dbm ?30dbm ?40dbm 1 1287-029 figure 29 . output response to rf burst input, carrier frequency = 2.14 ghz, c rms = 1 nf 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output (v) time (ms) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 rf burst pulse 0dbm ?10dbm ?20dbm ?30dbm ?40dbm 1 1287-030 figure 30 . output response to rf burst input, carrier frequency = 2.14 ghz, c rms = 0.1 f 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (s) 0 2 4 6 8 10 12 14 16 18 20 22 output vo lt age (v) 0dbm ?10dbm ?20dbm ?30dbm ?40dbm t adj/pwdn pulse 1 1287-031 figure 31 . output response using power - down mode for various rf input levels , carrier frequency = 2.14 ghz, c rms = 1 nf 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 output vo lt age (v) time (ms) t adj/pwdn pulse 0dbm ?10dbm ?20dbm ?30dbm ?40dbm 1 1287-032 figure 32 . output response using power - down mode for various rf input levels , carrier frequency = 2.14 ghz, c rms = 0.1 f
adl5906 data sheet rev. 0 | page 14 of 32 0 20 40 60 80 100 120 140 160 180 200 220 240 100 1k 10k 100k 1m 10m noise spectra l densit y (nv/hz) frequenc y (hz) 1 1287-033 figure 33 . noise spectral density of v rms , p in = ?10 dbm, ? 35 dbm , and ? 60 dbm ( no change in nsd vs. p in ), c rms = 0.1 f ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 ?55 ?35 ?15 5 25 45 65 85 105 125 error (c) v temp (v) temper a ture (c) 1 1287-034 figure 34 . v temp and linearity error with respect to straight line vs. temperature for typical device 1.32 1.34 1.36 1.38 1.40 1.42 1.44 count 1000 800 600 400 200 0 v temp vo lt age (v) 1 1287-035 represents 4500 p arts figure 35 . distribution of v temp at 25c, no rf input ?40 ?30 ?20 ?10 0 10 20 30 40 change in v ref (mv) ?55 ?35 ?15 5 25 45 65 85 105 125 temper a ture (c) 1 1287-036 figure 36 . change in v ref vs. temperature with respect to 25c, p in = ?40 dbm count 1000 800 600 400 200 0 2.25 2.26 2.27 2.28 2.29 2.30 2.31 2.32 v ref bias vo lt age (v) 1 1287-037 represents 4500 p arts figure 37 . distrib ution of v ref at 25c, no rf input 0.1 1 10 100 1.20 1.25 1.30 1.35 1.40 1.45 supp l y current (ma) v pwdn (v) v pwdn increasing 1 1287-038 v pwdn decreasing figure 38 . supply current vs. v pwdn
data sheet adl5906 rev. 0 | page 15 of 32 50 55 60 65 70 75 80 85 90 ?55 ?35 ?15 5 25 45 65 85 105 125 supp l y current (ma) temper a ture (c) 1 1287-004 figure 39 . supply current vs. temperature r e t urn l o ss ( d b ) s t ar t 10 m h z s t o p 10 g h z 1 g h z / d i v ? 30 ?2 0 ?1 0 10 0 1 1287-040 figure 40 . return loss at rf input port, 10 mhz to 10 ghz
adl5906 data sheet rev. 0 | page 16 of 32 theory of operation the adl5906 is functionally nearly identical to the adl5902 but has a broader frequency range ( 1 0 mh z to 10 ghz ). it is a true rms responding detector with a 67 db measurement range at 2.14 ghz and a greater than 57 db measurement range at frequencies up to 5.8 ghz. it is pin compatible with the adl5902 and ad8363 . transfer function peak - to - peak ripple is < 0. 3 db over the entire dynamic range. temperature stability of the rms output measurements provide s < 1 db error typical over the temperature range of ? 40 c to + 125 c up to 3.5 ghz. the device accurat ely measures waveforms that have a high peak - to - rms ratio (crest factor). the adl5906 consist s of a high performance automatic gain control ( agc ) loop. as shown in figure 41 , the agc loop comprises a wide bandwidth variable gain amplifier (vga), square law detectors, an amplitude target circuit, and an output driver. the nomenclature used in this data sheet to distinguish between a pin name and the signal on that pin is as follows: ? the pin name is all upper case , for example, crms , vset , and vrms . ? the signal name or a value associated with that pin is the pin mnemonic wit h a partial subscript, for example, c rms , v set , and v rms . square law detector and amplitude target the vga gain has the form g set = g o e ) / ( gns set v v ? (1) where: g o is the basic fixed gain. v gns is a scaling voltage that defines the gain slope ( the decibel change per voltage). the gain decreases with increasing v set . the vga output is v sig = g set rf in = g o rf in e ) / ( gns set v v ? (2) w here rf in is the ac voltage applied to the input terminals of the adl5906 . the output of the vga, v sig , is applied to a wideband square law detector. the detector provides the true rms response of the rf input signal, independent of waveform. the detector output, i sqr , is a fluctuating current wi th a positive mean value. the difference between i sqr and an internally generated current, i tgt , is integrated by the parallel combination of c f and the external capacitor attached to the crms pin at the summing node. c f is an on - chip 2 6 pf filter capacito r, and c rms , the external capacitance connected to the crms pin, can be used to arbitrarily increase the averaging time while trading off with the response time. when the agc loop is at equilibrium mean ( i sqr ) = i tgt (3) this equilibrium occurs only when me an ( v sig 2 ) = v tgt 2 (4) where v tgt is the voltage presented at the vtgt pin. this pin can conveniently be connected to the vref pin through a voltage divider to establish a target rms voltage , v atg , of ~40 mv rms when v tgt = 0.8 v. because the square law de tectors are electrically identical and well matched, process and temperature depende nt variations are effectively cancelled. t adj / p w d n band g a p r e f e r e nc e vrms vtemp ( 1 . 4 v) v r e f ( 2 . 3 v) i s q r i t g t x 2 x 2 g se t c rms (ex t e rna l ) c f ( i n t e rna l ) v s i g v g a s u mm i n g n o d e vset c h ( i n t e rna l ) vpos1/vpos2 gnd1/gnd2 rfin+ rfin t empe ra t ur e c o mpe n s a tio n and b i a s t empe ra t ur e se n s o r v t g t c rms v a t g = v t g t 2 0 1 1287-041 figure 41 . simplified architecture details
data sheet adl5906 rev. 0 | page 17 of 32 when forcing the previous identity by varying the v ga setpoint, it is apparent that rms ( v sig ) = ( mean ( v sig 2 )) = ( v atg 2 ) = v atg (5) substituting the value of v sig from equation 2 results in rms ( g 0 rf in e ) / ( gns set v v ? ) = v atg (6) when connected as a measurement device, v set = v rms . solving for v rms as a function of rf in , v rms = v slope log 10 ( rms ( rf in )/ v z ) (7) where: v slope = 1 .12 v/decade (or 5 6 mv/db) at 2.14 ghz . v z is the intercept voltage. when rms(rf in ) = v z , this implies that v rms = 0 v because log 10 (1) = 0. this makes the intercept the input that forces v rms = 0 v if the adl5906 had no sensitivity limit . in most applications, the agc loop is closed through the s etpoint interface and the vset pin. in measurement m ode , vrms is directly connected to vset ( s ee the measurement mode basic connections s ection for more information ) . in controller mode , a control voltage is applied to vset , and the vrms pin typically drives the control input of an amplification or attenuation syste m. in this case, the voltage at the vset pin forces a signal amplitude at the rf inputs of the adl5906 that balances the system through feedback. rf input interface figure 42 shows the rf input connections within the adl5906 . two internal 2.5 k ? resistors connected between rfin+ and rfin? primarily set t he input impedance. a dc level of approxima tely half the supply voltage on each pin is established internally at the center point of the bias resistors . either the rfin+ or the rfin ? pin can be used as the single - ended rf input pin. connect s ignal coupling capacitors from the input signal to the rf in+ and rfin ? pins. a single external 60.4 ? resistor to ground from the desired input create s an equivalent 50 ? impedance over a broad section of the operating frequency range. rf ac - couple t he other input pin to common (ground). the input signal high - pa ss corner formed by the internal and external resistances of the input coupling capacitor is f highpass = 1/(2 50 c ) ( 8 ) where c is the capacitance in farads , and f highpass is in hertz. the input coupling capacitors must be large enough in value t o pass the input signal frequency of interest and determine the low end of the frequency response. rfin+ and rfin ? can also be driven differentially using a balun. esd esd esd esd esd esd esd esd esd esd esd esd esd rfin? rfin+ vpos vbias gnd load n? n? 1 1287-141 figure 42 . rf inputs e xtensive esd protection is employed on the rf inputs , and this protection limit s the maximum possible input to the adl5906 . temperature sensor i nterface the adl5906 provides a temperature sensor output with a scaling factor of the output voltage of approximately 4. 8 mv/c. the output is capable of sourcing 4 ma and sinking 50 a maximum at 25c . an external resistor can be connected from v temp to gnd to provide additional curren t sink capability. the typical output voltage at 25c is approximately 1.4 v . vtem p vpos gnd interna l vpa t n? n? 1 1287-042 figure 43 . temp interface simplified schematic vref interface the vref pin provides an internally generated voltage reference for the user. the vref voltage is a temperature stable 2.3 v reference that is capable of sourcing 4 ma and sinking 50 a maximum. an external resistor can be connected from vref to gnd to provide additional current sink capability. the voltage on this pin can be used to drive t he tadj /pwdn and vtgt pins . interna l volt age n? vref vpos gnd 1 1287-143 figure 44 . vref interface simplified schematic
adl5906 data sheet rev. 0 | page 18 of 32 temperature compensa tion interface the adl5906 has a tadj pin that provides the ability t o optimize temperature performance using proprietary techniques as in the adl5902 . just like the adl5902 , the adl5906 has dual functionality on p in 1 , tadj / pwdn ; however, the pwdn function was redesigned to be dri ven by cmos logic as low as 1.8 v . for more detail on the power - down interfac e , see the power - down interface section. for optimal performance, the output temperature drift must be compensated using the tadj pin. the absolute value of compensation varies with frequency and vtgt. for recommen ded v tadj values at popular frequencies, see the setting vtadj section . one difference in the temperature compensation of the adl5906 compared to the adl5902 is that v tadj adjusts the slope of the detector, and with the adl5902 , the intercept was adjusted. adjusting the slope was found beneficial to locking in temperature drift and thereby producing parallel error curves over most frequencies. any remaining intercept temperature drift can then be reduced in the digital domain after sampling v rms because the intercept drift is quit e repeatable at frequencies up to approximately 5 .8 ghz ( s ee the using v temp to improve intercept temperature drift section) . there is a trade - off in setting values , and optimizing for one area of the dynamic rang e may mean less than optimal drift performance at other input amplitudes. in addition, different voltages applied to the vtgt pin impact drift; all tadj voltages shown in the performance curves were determined with a vtgt of 0.8 v. for vtgt values that do not deviate too far from the nominal 0.8 v , and for frequencies up to approximately 5 ghz, it is expected that the tadj voltages are a good starting point for the best temperature drift compensation. compensating the device for temperature drift using v tad j allows for great flexibility. if the user requires minimum temperature drift at a given input power, a subset of the dynamic range, or even over a different temperature range than shown in this data sheet, the v tadj can be swept while monitoring v rms ove r the temperature at the frequency and amplitude of interest. the optimal v tadj to achieve minimum temperature drift at a given power and frequency is the value of v tadj where the output has minimum movement. 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55 3.60 3.65 3.70 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 output vo lt age (v) v t adj vo lt age (v) 1 1287-043 figure 45 . effect o f v tadj at various temperatures, 2 .14 g hz, 0 dbm var yi ng v tadj has only a very slight effect on vrms at device temperatures near 25c; however, the compensation circuit has increasing effect as the temperature departs farther from 25c. it is important t o note that the slope is adjusted vs. temperature. the pivot point of this is at low input power levels and thereby move s the v rms output more at larger input signal levels; that is, near maximum input power, the temperature drift can be minimized the most . this is advantageous in most power measurement cases because errors at larger powers tend to have more of a negative effect. the tadj /pwdn pin has a nominal input resistance of 70 k ? and can be conveniently driven from an external source or from an atten uated value of vref using a resistor divider . the resistor s are shown in the evaluation board schematic (see figure 63). the voltage range for v tadj is from 0 v to approximately 1 .0 v because approximately 1.3 v is the logic t hreshold for power down of the device.
data sheet adl5906 rev. 0 | page 19 of 32 power - down interface figure 46 shows a simplified schematic representation of the tadj/pwdn interface. the quiescent and power - down currents for the adl5906 at 25c are approximately 68 ma and 2 5 0 a, respectively. the dual function tadj /pwdn pin is connected to the temperature compensation circuit as well as the power - down circuit. th e temperature compensation circuit res p onds only to voltages between 0 v and 1 v. w hen the voltage on this pin is greater than ~ 1. 4 v, t h e device is fully powered down. figure 38 shows this characteristic as a func tion of v pwdn . the tadj /pwdn pin with an internal 70 k ? resistor to ground sink s approximately 26 a at 1.8 v , 47 a at 3.3 v , and 7 2 a at 5 v . the source used to disable the adl5906 must have a sufficiently high current capability for this reason. figure 31 shows the typical response times for various rf input levels. the output reac hes within 1 db of its steady state value in approximately 12 s for c rms = 1 nf ; however, the reference voltage is available to full accuracy in a much shorter time. this wake - up response varies depending on the input coupling and the value of c rms . temper a ture compens a tion circuit esd esd t adj/ pwdn vpos gnd t adj maximum oper a ting vo lt age = 1v esd 50k ? pwd = pwdn logic threshold ~1v 0.1v logic threshold ~1.3v 0.1v 5 7 20k ? 1k ? 1k ? 70k ? shutdown circuit 1 1287-044 fi gure 46 . tadj /pwdn interface simplified schemati c vset interface the vset interface has a high input impedance of 72 k?. the voltage at vset is converted to an internal current used to set the internal vga gain. the vga attenuatio n control is approximately 18 d b / v. gnd 1k? 9k? vset 63k ? gain adjust 1 1287-045 figure 47 . vset interface simplified schematic output interface the adl5906 incorporates rail - to - rail output drivers with pull - up and pull - down capabilities. the level shift circuitry and the output amplifier are very fast compared to the typical rms response required by a complex waveform. in essence, the output stage from the crms pin to the vrms output is only a dc signal becau se by definition v rms is supposed to be a single rms value. the vrms pin can source and sink up to 10 ma. leve l shift circuit r y esd crms vrms esd vpos gnd esd crms externa l 26pf ~2.1v dc bias i tgt i sqr 2k ? 500 ? 1 1287-046 figure 48 . vrms interface simplified schematic vtgt interface the target voltage can be set with an external source or by connecting the vref pin (nominally 2.3 v) to the vtgt pin through a resistive voltage divider. with 0.8 v on the vtgt pin, the rms voltage that must be provided by the vga to balance the agc feedback loop is 0.8 v 0.05 = 40 mv rms. most of the characteri zation information in this data sheet was collected at v tgt = 0.8 v. voltages higher and lower than this can be used; however, doing so increases or decreases the gain at the internal sq uaring cell, which results in a corresponding increase or decrease in intercept. this , in turn , affects the sensitivity and the usable measurement range, in addition to the sensitivity to different carrier modulation schemes . as v tgt decre ases, the squaring circuits produce more noise ; this become s noticeable in the output r esponse at low input signal amplitudes. as v tgt increases, measurem ent error due to modulation increase s , and temperature drift tend s to decrease. the chosen v tgt value of 0.8 v represents a compromise between these characteristics. vtgt 50 k? 50 k? 2 0 k? esd es d es d vpos gnd i tgt g x 2 1 1287-047 figure 49 . vtgt interface
adl5906 data sheet rev. 0 | page 20 of 32 basis for error calc ulations the slope and intercept used in the error plots are calculat ed using the coefficients of a linear regression performed on data collected in its central operating range. the error plots in the typical performance characteristics section are shown in two formats: error from the ideal lin e and e rror with respect to the 25c output voltage . the e rror from the ideal line is the decibel difference in v rms from the ideal straight - line fit of v rms calculated by the linear regression fit over the linear range of the detector, typically at 25c. the error in decibels is calculated by error ( db ) = ( v rms ? slope ( p in ? p z ))/ slope (9) where p z is the x - axis intercept expressed in decibels relative to 1 mw (the input amplitude that produce s a 0 v output if such an output were possible). the error from the ideal line is not a measure of absolute accuracy b ecause it is calculated using the slope and intercept of each device . however, it verifies the linearity and the effect of temperature and modulation on the response of the device. an example of this type of plot is figure 9 . the slope and intercept that form the ideal line are those at 25c with cw modulation. figure 4 , figure 5 , figure 7 , and figure 8 show the error with various popular forms of modulation with respect to the ideal cw line. this method for calculating error is accurate , assuming that each device is calibrated at room temperature. in the second plot format, the v rms voltage at a given input amplitude and temperature is subtracted from the corresponding v rms at 25c and then divided by the 25c slope to obtain an error in decibels. this type of plot does not provide any information on the linear - in - db performance of the device; it merely shows the decibel equivalent of the deviation of v rms over temperature, given a calibration at 25c. when calculating error from any one particular calibration point, this error format is accurate. i t is accurate over the full range shown on the plot assuming that enough calibration points are used. figure 12 shows this plot type . the error calculations for figure 34 are similar t o th ose for the v rms plots. the slope and intercept of the v temp function vs. temperature are determined and applied as follows: error ( c ) = ( v temp ? slope ( temp ? t z ))/ slope (1 0) where: v temp is the voltage at the temp pin at that temperature. slope is , typically, 4. 8 mv/c. te mp is the ambient temperature of the adl5906 in degrees celsius. t z is the x - axis intercept expressed in degrees celsius (the temperature that would result in a v temp of 0 v if this were possible). measurement mode bas ic connections the basic connections circuit for adl5906 is shown in figure 51 . the adl5906 requires a single supply of nominally 5 v. the supply is connected to the vpos 1 and vpos2 supply pins . decouple each of t he se pin s using two capacitors with values equal or similar to those shown in figure 51 . place t hese capacitors as close as possible to the vpos pins. the three no connect pins (ni c) are not internally connected . leave these pins unconnected. an external 60 .4 resistor combines with the relatively high rf input impedance of the adl5906 to provid e a broadband 50 match. place a n ac coupling capacitor between this resistor and rfin+ . ac - couple t he rf in ? input to ground using the same value capacitor. to operate down to 10 mhz, the coupling capacitors must be at least 100 pf. the adl5906 is placed in measurement m ode by connecting the vrms pi n to the vset pin . in measurement m ode, the output voltage is proportional to the log of the rms input signal level. setting v tadj as d escribe d in the theory of operation section, the output temperature drift can b e compensated by applying a voltage to the tadj pin. the compensating voltage varies with frequency. the voltage for the tadj pin can be easily derived from a resistor divider connected to the vref pin. table 4 sho ws the recommended v tadj voltages for operation from ? 55 c to + 125 c, along with resistor divider values. resistor values are chosen so that they neither pull too much current from the vref pin (i outmax = 4 ma) nor are so large that the maximum bias curren t at a v tadj = 1 v ( 14 a) affects the resulting voltage. the v tadj function provides temperature compensation of the output slope of the adl5906 . the using v temp to imp rove intercept temperature drift section describes how the temperature stability of the adl5906 can be further improved. table 4 . recommended v tadj voltages frequency v t adj (v) r9 (?) r12 (?) 10 mhz to 2.14 ghz 0.35 1500 270 2.6 ghz 0.4 1500 316 3.5 ghz 0.45 1500 365 5.8 ghz 1.0 1540 1200 8 ghz 1.0 1540 1200 10 ghz 1.0 1540 1200
data sheet adl5906 rev. 0 | page 21 of 32 setting v tgt as d escrib ed in the theory of operation section, setting the voltage on vtgt to 0.8 v represents a compromise between a chieving excellent rms accuracy and maximizing dynamic range . the voltage on vtgt can be derived from the vref pin using a resistor divider , as shown figure 51 . like the resistors chosen to set the v tadj voltage, the resistors setting v tgt must have reasonable values that do not pull too much current from vref or cause bias current errors. in addition , note the combined current that vref must deliver to generate the v tadj and v tgt voltages . t he values shown in figure 51 and table 4 result in a maximum vref current of 1.7 ma . this current is well below the maximum specified vref current of 4 ma. choosing a value for c rms c rms provides the averaging function for the internal rms computation. using the minimum value for c rms allows the quickest response time to a pulsed waveform but leaves significant output n oise on the output voltage signal. by the same token, a large filter capacitor reduces output noise but at the expense of response time. in applications where response time is not critical, a relatively large capacitor can be placed on the crms pin. in figure 51 , a value of 0.1 f is used. for most signal modulation schemes, this value ensures excellent rms measurement compliance and low residual output noise. there is no maximum capacitance limit for c rms . figure 50 shows how output noise varies with c rms when the adl5906 is driven by a single - carrier w - cdma signal (test model tm1 - 64, peak envelope power = 10.56 d b, bandwidth = 3.84 mhz). 0.1 1 10 100 1000 10000 100000 1000000 0 50 100 150 200 250 300 350 1 10 100 1000 10000 rise time/ f al l time (s) output noise (mv p-p) c rms (nf) output noise (v p-p) rise time (s) f al l time (s) 1 1287-049 figure 50 . output noise, rise and fall times vs. c rms capacitance, single - carrier w - cdma (tm1 - 64) at 2.14 ghz with p in = 0 dbm figure 50 also shows how the re sponse time is affected by the value of c rms . to measure this, an rf burst at 2.14 ghz at 0 dbm was applied to the adl5906 . the 10% to 90% rise time and 90% to 10% fall time were then measured. c9 0.1f (see text) (and t able) r9 (see text) (and t able) x 2 bias and power down contro l 1 nic i tgt linear-in-db vg a (neg a tive slope) i sqr 26pf 2 vpos1 vpos2 3 gnd1 vref vtg t gnd2 4 1 1 1 0 9 5 crms 6 vrms vrms 7 v se t 8 1 6 1 5 1 4 1 3 vtem p nic rfin? rfin+ ni c epad adl5906 1 2 x 2 v ref 2.3v temper a ture sensor g = 5 r3 60.4? c10 10nf rfin c12 10nf r12 r1 1 2k? r10 3.74k? +5v c3 0.1f c4 100pf c7 0.1f c5 100pf +5v 1 1287-148 t adj/ pwdn figure 51 . basic connections for operation in measurement mode
adl5906 data sheet rev. 0 | page 22 of 32 table 5 . recommended minimum c rms values for various modulation schemes modulation/standard peak envelope power ratio (db) carrier bandwidth (mhz) c rmsmin (nf) output noise (mv p - p) rise/fall tim e (s) qpsk , 5 msps (sqr cos filter, = 0.35) 3.8 5 1 84 0.2/10 qpsk , 15 msps (sqr cos filter, = 0.35) 3.8 15 1 42 0.2/10 64 qam , 1 msps (sqr cos filter, = 0.35) 7.4 1 10 265 3/85 64 qam , 5 msps (sqr cos filter, = 0.35) 7.4 5 1 380 0.2/10 64 qam , 13 msps (sqr cos filter, = 0.35) 7.4 13 1 205 0.2/10 w - cdma, one - carrier, tm1 -64 10.56 3.84 1 820 0.2/10 w - cdma four - carrier, tm1 - 64, tm1 - 32, tm1 - 16, tm1 - 8 12.08 18.8 4 1 640 0.2/10 lte, tm1 , one - carrier, 20 mhz (2048 qpsk subcarriers) 11.58 20 1 140 0.2/10 table 5 shows the recommended minimum values of c rms for popular modulation schemes . using lower capacitor values results in r ms measurement errors. output response time is also shown. if the output noise shown in table 5 is unacceptably high, it can be reduced by ? increasing c rms ? implementing an averaging algorithm after the output voltag e of the adl5906 has been sampled by an analog - to - digital converter ( adc ) th e value s in table 5 were experimentally determined to be the minimum capacitance that ensures good rms accuracy for that particular signal type . this test was carried out by starting out with a large capacitance value on the crms pin ( for example, 10 f). the value of v rms was noted for a fixed input power level ( for example, ? 10 dbm). the value of c rms was then progressively reduced (this can be done with press - down capacitors) until the value of v rms started to deviate from its original value (this indicates that the accur acy of the rms computation is degrading and that c rms is becom ing too small). in general , the minimum required rms averaging capacitance increase s as the peak - to - average ratio of the carrier increases. the minimum required c rms also tend s to increase as th e bandwidth of the carrier decreases. w ith narrow - band carriers, the noise spectrum of the v rms output tends to have a correspondingly narrow profile. the relatively narrow spectral profile demands a larger value of c rms that reduces the low - pass corner fr equency of the averaging function and ensures a valid rms computation. output v oltage scaling the linear output voltage range of the adl5906 is nominally 0.3 v to 3. 7 v . v rms is clamped to a max imum voltage of ~ 3.9 v ; this helps improve falling edge settling speeds because the v rms output stays closer to the nominal linear - in - db output range of 0.3 v to 3.7 v. within the 0 v to 3.9 v maximum output range, the slope can be adjusted as needed via e xtra resistors , as shown in figure 52. if only a part of the rf input power range of the adl5906 is being used ( for example, ? 10 dbm to ? 60 dbm) , increase the scaling so that this reduced input range fits into the available output swing ( 0 v to 3.9 v ) of the adl5906 . the output swing is reduced by simply add ing a voltage divider on the output pin , as shown in the a side of figure 52 . reducing the output scaling can be used when interfacing the adl5906 to an adc with a 0 v to 2.5 v input range. 6 7 vs e t r6 r 2 vrms 6 7 vs e t a b r 1 r15 vrms 1 1287-149 figure 52 . decreasing and increasing slope the output voltage swing can be increased using a technique that is analogo us to setting the gain of an op amp in noninverting mode (see the b side of figure 52) with the vset pin being the equivalent of the inverting input of the op am p . with vrms connected to vset, the nominal transfer function of the adl5906 is given by v rms = slope ( p in ? intercept ) for example at 3.5 ghz, with p in equal to 0 dbm , the nominal output voltage is equal to 0.052 v/db (0 dbm ? ( ? 64 dbm) = 3.328 v . to scale this voltage downward using a resistor divider, choose a value for r15 and calculate r1 us ing the following equation : ? ? ? ? ? ? ? ? ? = 1 ' rms rms v v r15 r1 (1 1 )
data sheet adl5906 rev. 0 | page 23 of 32 to scale this voltage upward , choose a value for r2 and calculate r6 using the following equation : ? ? ? ? ? ? ? ? ? = 1 ) || ( rms ' rms in v v r r2 r6 (1 2 ) w here : r in is the input resistance of vset (72 k?). v' rms is the de sired maximum output voltage. v rms is the n ominal maximum output voltage before scaling (see figure 9 through figure 26) . when choosing r1 , r2, r6 , and r15 , notice the curr ent drive capability of the vrms pin and the input resistance of the v set pin . the choice of resistors must not be too small because this result s in excessive current draw n out of the vrms pin (the vrms pin can source a maximum current of 10 ma) . however, choosing an r 2 that is too large is also problematic. if the value of r2 chosen is compatible with the input resistance of the v set pin (72 k ? ) , this input resistance, which var ies slightly from part to part , contribute s to the resulting slope and output v oltage. in general, ensure that the value of r2 is at least 10 times smaller than the input resistance of vset . therefore, the v alues for r 6 and r2 must be in the 1 k to 5 k range. similar values must be used for r1 and r15. it is also important to take into account part - to - part and frequency variation in outpu t swing along with the maximum output voltage ( 3.9 v ) of the output stage of the adl5906 . the v rms part - to - part distribution is well cha racterized at major frequenc y bands in the typical performance characteristics section (see figure 12 through figure 14, figure 18 through figure 20 , figure 24 , and figure 25) . the resistor values in table 6 , which were calculated based on 3.5 ghz operation , have been con servatively chosen so that there is no chanc e that the desired output voltage swings exceed the output swing of the adl5 906 (when scaling upward) or the input range of a 0 v to 2.5 v adc (when scaling down - ward) . in each case , the nominal maximum voltage that results is 100 mv below the desired maximum to account for part - to - part variation and resistor tolerances. table 6 . output voltage range scaling example s at 3.5 ghz desired input range (dbm) slope increase slope decrease new slope (mv/db) nominal maximum output voltage (v) r6 (?) r2 (?) r1 (?) r15(?) 0 to ?60 274 2000 59 3.8 ?10 to ?50 681 2000 70 3.8 0 to ?60 787 2000 37 2.4 ?10 to ?50 348 2000 44 2.4
adl5906 data sheet rev. 0 | page 24 of 32 system calibration a nd error calculation the measured transfer function of the adl5906 at 2.14 ghz is shown in figure 53 , which contains plots of both output voltage vs. input level and linearity error vs. input level . as the input level varies from ? 65 dbm to +5 dbm, the output voltage varies from ~0.25 v to ~ 3 .9 v. ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age (v) p in (dbm) 1 1287-051 output vo lt age ?4 0 c output vo lt age +2 5 c output vo lt age +8 5 c error ?4 0 c error +2 5 c error +8 5 c figure 53 . 2.14 ghz v rms and log conformance error at +25c, ?40c, and +85c u sing two - point calibration at 0 dbm and ? 40 dbm because slope and intercept vary from devi ce to device, board level calibration must be performed to achieve high accuracy. the equation for the idealized output voltage can be written as v rms (ideal) = slope ( p in ? intercept ) (1 3 ) where: slope is the change in output voltage divided by the chan ge in input power (db). intercept is the calculated input power level at which the output voltage is equal to 0 v (n ote that intercept is an extrapolated theoretical value and not a measured value). in general, calibration is performed during equipment ma nufacture by applying two or more known signal levels to the input of the adl5906 and measuring the corresponding output volta ges. the calibration points must be within the linear operating range of the device. with a two - p oint calibration, the slope and intercept are calculated as follows: slope = ( v rms 1 ? v rms 2 )/( p in1 ? p in2 ) ( 14) intercept = p in1 ? ( v rms 1 / slope ) ( 15) after the s lope and i ntercept are calculated and stored in nonvolatile memory during equipment calibration, an equation can be used to calculate an unknown input power based on the output voltage of the detector. p in ( u nknown ) = ( v rms (measured) / slope ) + intercept ( 16) the log conformance error is the difference between this str aight line and the actual performance of the detector. error ( db ) = ( v rms ( measured ) ? v rms ( ideal ) )/ slope ( 17) figure 53 includes a plot of this error at + 25 c, ? 40 c , and +85 c when using a two - point calibration (c alibration p oints are 0 dbm and ? 40 dbm). the error at the calibration points at 25 c (in this case, ?40 dbm and 0 dbm) is equal to 0 db by definition . the residual non linearity of the transfer function that is apparent in the two - p oint c al ibration error plot can be reduced by increasing the number of calibration points. figure 54 s hows the post - calibration error plots for a three - p oint calibration. with a mult i point calibration, the transfer function is segmented , wi th each s egment having its own slope and intercept. multiple known po wer levels (three levels in this case) are applied , and multiple voltages are measured. when the equipment is in operation, the measured voltage from the detector is first used to determine which of the stored slope and i ntercept calibratio n coefficients a re to be used. then , the unknown power level is calculate d by inserting the appropriate s lope and i ntercept values into equation 16. when choosing calibration points, there is no requirement for, or value in , equal spacing between the points. there is also no limit to the number of calibration points used. however , when more calibration points are used, calibration time increases . output vo lt age (v) p in (dbm) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) output vo lt age ?4 0 c output vo lt age +2 5 c output vo lt age +8 5 c error ?4 0 c error +2 5 c error +8 5 c 1 1287-152 v t adj = 0.35v figure 54 . 2.14 ghz v rms and log conformance error at + 25 c, ? 40 c , and +85 c using three - point calibration at 0 dbm, ? 40 dbm , and ? 55 dbm the ? 40 c and +85 c error plots in figure 54 are generated using the + 25 c slope and intercept values . this is consistent with equipmen t calibration in a mass production environment where calibration of multiple temperatures is not practical .
data sheet adl5906 rev. 0 | page 25 of 32 u sing v temp to improve intercept temperature drift in applications where v temp and v rms are both being digitized by an adc, the v temp voltage can be used to further improve the temperature drift of the adl5906 . as shown in figure 54, whe reas the s lope is stable vs. the temperature at 2140 mhz, the intercept of the adl5906 does vary slightly vs. temperature (approximately +0.3 db at +85 c and ? 0.8 db at ? 40 c). this variation in i ntercept is constant vs. input power level a t most frequencies. table 7 lists the average temperature coefficient of v rms in mv/ c at frequencies from 100 mhz to 5.8 ghz. this temperature coefficient is given by the following equation : tc vrms = ( drift vrms / t emp ) s lope ( 18) w here : drift vrms is the specified drift of v rms (scaled in db) from ambient to either ? 40 c or +85 c at an input power level of 0 dbm (see table 1 ) . ? temp is equal to either + 65 c for cold drift ( that is, +25 c ? ( ? 40 c)) or +60 c for hot drift ( that is, +85 c ? +25 c) . s lope is the specified slope of v rms ( see table 1 ). for example, a t 2.14 ghz , tc vrms for hot drift can be calculated as tc vrms = (0.3 db/60 c) 56 mv/db = 0.28 mv/ c the value for slope that is used can also be the s lope that is calculated during device calibration. this give s results that are slightly more accurate because there is slight variation in s lope from device to device. table 7 also l ists the typical temperature coefficient of the v temp temperature sensor output. to calculate the appropriate amount of compensation required at a particular frequency, a v temp weighting factor is calculated. this is simply the ratio of the temperature coe fficients of vtemp and vrms. these weighting factors are also shown in table 7 . u sing the data shown in table 7 , an adjusted value for v rms (v rms ) can be calculated using the following e quation : ? ? ? ? ? ? ? ? ? ? = factor weighting v v v ' v temp25 temp rms rms ( 19) w here : v temp25 is equal to the voltage measured on v temp during system calibration at ambient temperature. v temp is equal to the voltage on v temp during normal operation. figure 55 to figure 62 sho w typical plots of v rms vs. input level and temperatur e at frequencies from 100 mhz to 5.8 ghz when this temperature compensation algorithm is applied. from a system calibration and operation perspective, the only addi tional measurements that are required to implement this algorithm are measurement and storage of v temp during calibration ( that is, at ambient temperature) and measurement of v temp during operation. all other information required to implement this algorith m ( that is, nominal temperature drift of v rms and temperature coefficient of v temp ) is based on typical data sheet specifications. ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) v rms ' (v) p in (dbm) v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c 1 1287-153 v t adj = 0.35v figure 55 . v rms and log conformance error vs. input level and temperature at 100 mhz using v temp intercept compensation ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 p in (dbm) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 error (db) v rms ' (v) v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c 1 1287-054 v t adj = 0.35v figure 56 . v rms and log conformance error vs. input level and temperature at 700 mhz using v temp intercept compensation
adl5906 data sheet rev. 0 | page 26 of 32 ?6 5 ?5 5 ?4 5 ?3 5 ?2 5 ?1 5 ? 5 5 p i n ( d b m ) ? 6 ? 5 ? 4 ? 3 ? 2 ? 1 0 1 2 3 4 5 6 0 0 . 5 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 6 . 0 e rr o r ( d b ) v rms ' (v) 1 1287 - 15 5 v rms ' ?40 c v rms ' + 25 c v rms ' + 85 c e rr o r ?40 c e rr o r + 25 c e rr o r + 85 c v t adj = 0.35v figure 57 . v rms and log conformance error vs. input level and temperature at 900 mhz using v temp intercept compensation p in (dbm) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) v rms ' (v) v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c 1 1287-156 v t adj = 0.35v figure 58 . v rms and log conformance error vs. input level and temperature at 1900 mhz u sing v temp intercept compensation p in (dbm) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) v rms ' (v) 1 1287-057 v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c v t adj = 0.35v figure 59 . v rms and log conformance error vs. input level and temperature at 2140 mhz using v temp intercept compensation p in (dbm) ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) v rms ' (v) v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c 1 1287-058 v t adj = 0.4v figure 60 . v rms and log conformance error vs. input level and temperature at 2600 mhz u sing v temp intercept c ompensation ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) v rms ' (v) p in (dbm) 1 1287-059 v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c v t adj = 0.45v figure 61 . v rms and log conformance error vs. input level and temperature at 3500 mhz u sing v temp intercept compensation ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 error (db) v rms ' (v) p in (dbm) 1 1287-060 v rms ' ?40c v rms ' +25c v rms ' +85c error ?40c error +25c error +85c v t adj = 1v figure 62 . v rms and log conformance error vs. input level and temperature at 5800 mhz u sing v temp intercept compensation
data sheet adl5906 rev. 0 | page 27 of 32 table 7 . scaling factors for intercept temperature drift compensation u sing v temp freq uency (mhz) tc vrms , ? 40 c to +25 c , p in = 0 dbm (mv/ c) tc vrms , 25 c to 85 c , p in = 0 dbm (mv/ c) tc vtemp (mv/ c) v temp weighting factor , ? 40 c to +25 c (tc vtemp /tc vrms ) v temp weighting factor , +25 c to +85 c (tc vtemp /tc vrms ) 100 0.72615 0.19667 4.8 6.61017 24.40678 700 0. 81692 0.295 4.8 5.87571 16.27119 900 0.72615 0.295 4.8 6.61017 16.27119 1900 0.70154 0.19 4.8 6.84211 25.26316 2140 0.68923 0.28 4.8 6.96429 17.14286 2600 0.76154 0.275 4.8 6.30303 17.45455 3500 1.2 0 4.8 4 5800 1.2393 1 0.0804 1 4.8 5.99417 85.287 1 tc vrms based on temperature drift at p in = ? 10 dbm . description of chara cterization for a description on how characterization was completed , see the adl5902 data sheet.
adl5906 data sheet rev. 0 | page 28 of 32 evaluation board the adl5906 - e va l z is a fully populated, 4 - layer, fr4 - based evaluation board. for normal operation, it requires a 5 v/100 ma power supply. the 5 v power supply must be connected to the vpos and gnd test loops . the rf input signal is applied to the sma connector ( rfin ) . the output voltage is available on the sma connector ( v out 1 ) or on the test loop ( v out ) . configuration options for the evaluation board are listed in table 8 . x 2 bias and power down contro l 1 nic i tgt linear-in-db vg a (neg a tive slope) i det 26pf 2 vpos1 vpos2 3 gnd1 vref vtgt gnd2 4 1 1 1 0 9 5 crms c9 0.1f 6 vrms 7 vset 8 1 6 1 5 1 4 1 3 vtem p nic rfin? rfin+ nic ep ad adl5906 1 2 x 2 v ref 2.3v temper a ture sensor g = 5 r3 60.4? c10 10nf rfin tc2 vout vout1 vref vtgt gnd c12 10nf r12 270? r9 1.5k? r1 1 2k? r10 3.74k? r6 0? r1 0? r2 (open) r15 (open) vset vpos c3 0.1f c4 100pf c7 0.1f c5 100pf 1 1287-150 t adj/ pwdn figure 63 . evaluation board schematic table 8 . evaluation board configuration options component function/notes default value rfin, r3, c10, c12 rf i nput . the evaluation board is configured for single - ended drive on the rfin+ pin (pin 14). capacitors c10 and c12 have been set large enough so that the full frequency range of the device is covered. if operation down to 10 mhz is not required, the value of these capacitors can be reduced . rfin = sma c onnector , c10 = c12 = 1 0 nf , r3 = 60.4 ? vtgt, r10, r11 vtgt i nterface . r10 and r11 are set up to provide 0.8 v to vtgt derived from vref. if r10 and r11 are removed, an external voltage can be applied on the vtgt test point . vtgt = black test loop, r10 = 3.74 k?, r11 = 2 k? , vtgt = 0.8 v vpos, gnd , c3, c4 , c5,c7 power supply interface and decoupling . apply t he power supply for the evaluation board to the vpos and gnd test loops. the nominal supply decoupling consists of a 100 pf capacitor and a 0.1 f capacitor on each power supply pin, with the 100pf capacitor placed close r to the pin. vpos = red test loop, gnd = black test loop, c 3 = c 7 = 0.1 f , c4 = c5 = 100 pf
data sheet adl5906 rev. 0 | page 29 of 32 component function/notes default value vout, vout1, vset, r1, r2, r6, r15 output i nterface. in measurement mode, a portion of the voltage at the vrms pin is fed back to the vset pin via r6 (r6 is normally set to 0 ?). using the voltage divider created by r2 and r6, the magnitude of the slope of v rms is increased by reducing the portion of vrms that is fed back to vset. resistors r1 and r15 can be used to redu ce the output slope. vout = black test loop, vout1 = sma connector, vset = black test loop, r1 = r6 = 0 ?, r15 = r2 = open in controller mode, r6 must be open. in this mode, the adl5906 can c ontrol the gain of a variable gain amplifier (vga) or voltage variable attenuator (vva). a setpoint voltage is applied to the vset test loop , and the vrms test loop or sma connector drives the gain control input of the vga/vva. c9 rms averaging capacitor . the value of the rms averaging capacitor should be set based on the peak -to - average ratio of the input signal and based on the desired output response time and residual output noise. c9 = 0.1 f tc2, r9, r12 tadj/pwdn i nterface . the tadj /pwdn pin contr ol s the slope temperature compensation and/or shuts down the device. the evaluation board is configured with vtadj connected to vref throug h a resistor divider ( r9, r12). this voltage divider can be removed (or simply overdriven ) allowing for the external application of a voltage to the vtadj pin by applying a voltage to the tc2 test point . tc2 = black test loop, r 9 = 1 . 5 k ? , r12 = 270 ? , v tadj = 0.35 v evaluation board assembly drawings 1 1287-055 figure 64 . adl5906 evaluation board layout, top side 1 1287-056 figure 65 . adl5906 evaluation board layout, bottom side
adl5906 data sheet rev. 0 | page 30 of 32 outline dimensions compliant to jedec standards mo-220-wggc. 111908-a 1 0.65 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 0.70 0.60 0.50 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 0.35 0.30 0.25 2.25 2.10 sq 1.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 66 . 16 - lead lead frame chip scale package [lfcsp_ w q] 4 mm 4 mm body, very very thin quad (cp - 16 - 23 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity adl5906acpzn -r2 ?40c to +1 0 5c 16 - lead lead frame chip scale package [lfcsp_wq] cp -16-23 250 adl5906acpzn -r7 ?40c to +1 0 5c 16 - lead lead frame chip scale package [lfcsp_wq] cp -16-23 1,500 adl5906scpzn - r2 ?55c to +125c 16 - lead lead frame chip scale package [lfcsp_wq ] cp -16-23 250 adl5906scpzn - r7 ?55c to +125c 16 - lead lead frame chip scale package [lfcsp_wq] cp -16-23 1,500 adl5906 - evalz evaluation board 1 z = rohs compliant part.
data sheet adl5906 rev. 0 | page 31 of 32 notes
adl5906 data shee t rev. 0 | page 32 of 32 notes ? 2013 analog devices, inc. all rights reserved. tradema rks and registered trademarks are the property of their respective owners. d11287 - 0- 3/13(0)

▲Up To Search▲

Price & Availability of ADL5906-EVALZ

	To Download ADL5906-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .